• RE: DAS-9100 series and P6464 Logic Probe clock troubleshooting

    thanks for the lead.&nbsp; &nbsp;I'm not sure exactly how you're seeing that information, but i'll contact the Sales department, and see if I can get a quote.<br> <br> That part number is not "auto-populating" as a valid part number.
  • RE: DAS-9100 series and P6464 Logic Probe clock troubleshooting

    Oh sorry, the document did not attach.&nbsp; &nbsp;here is a web-link instead:&nbsp;&nbsp;<a href="https://w140.com/tekwiki/images/8/88/070-5397-00.pdf">070-5397-00.pdf (w140.com)</a>
  • DAS-9100 series and P6464 Logic Probe clock troubleshooting

    I'm having issues with an old Test System breaking down, and I'm wondering if anyone here might have (or know of someone) who has some working experience with these?

    Our problem, at the moment is that most of our P6464 Probes are operating correct at lower test speeds (below 10MHz, or the 100nS timing setting)....but when operating above that speed (up to 50MHz, or the 20nS timing) the Clock line is being skewed by a DC-offset which is putting the "low" side of the waveform -really close- to the no-go range for TTL level signals (about 2.0Vdc).    

    Before anyone goes there....yes, we have copies of the Service and Maintenance manuals (1985 and 1986 versions), and the addendum that specifies the Output limit specifications.   Our Probes are technically failing the low-side specification, per page 531 (1-32) of the attached manual, but there is no troubleshooting steps in the manual for the P6464 probes:

    VL Out = VL +0.80 V    

    It looks like the problem may be with the Hybrid chip in the probe itself (Tek part number:  165-2051-00), but there is absolutely no documentation of that chip in any of our hardcopy archives.    

    I know this is a long-shot ask, but hopeflly someone has a contact I may be able to reach-out to.   thansk,  ~Dan