2281S behavior starting up directly into CC-mode

I have 2281S-20-6, SW ver. 01.08

The setup are as such:

• Unit in PSU mode
• Set V-set at 8.0V, set I-set at 40mA
• Set slew rate at 1000V/s (unless specified otherwise)
• Set OVP at 21V and OCP at 6.1A
• Set output delays and source delays off or zero
• Output is disabled
• Connect output into 45Ω resistor as load
• Enable output

Expectation:

• Output voltage never exceed V-set
  • AND
• Output current never exceed I-set
  • Whichever is reached first (i.e. strict CV and CC operation)
• Output voltage should settle into 45Ω * 40mA = 1.8V

Observation:

• Output voltage continues to ramp up all the way to V-set before ramping down (see attachments)
  • 
• Output current grossly exceed I-set during the aforementioned spike.
• Reducing slew rate setting reduces the peak spike voltage (and current), but still exceeds I-set nonetheless.
  • 

Question:

• Is this intended behavior?
• Is there any way to mitigate this?

Interesting.  I think it is related to the starting up into CC mode.
Datasheet does not tell us, but the output capacitance on the power supply is significant.
Slower V/sec slew rate will mean less displacement current.
How are you measuring the current in this setup?  Hi side or lo side of the 45Ω resistor?

If your concern is too much current when started up this way, some series R and use of the remote sense lines from rear panel could help.  Just mind the max 1V delta V between force and sense.

 

Current is "measured" by Ohm's Law, as the load is a fixed 45R resistor, low inductance metal film. Changing from front panel to rear panel (with kelvin sensing) don't appreciably change the response.

Yes, this is (most likely) startup behavior. This particular initial overshoot is also observed in many other PSUs, especially newer one. For reference there's a thread on EEVBlog forum discussing this excursion: https://www.eevblog.com/forum/testgear/lab-power-supply-turn-on-and-off-characteristics/

However I don't think this is caused by output capacitor discharge, the waveforms don't match. As indicated by the stairstep and correct slew rate, the upslope is within the PSU control loop and the PSU should be able to control its output. It just doesn't appear to control the current until a certain time after output is enabled.

I agree that a proper test setup will include limiting resistor in series with DUT, and if I want tight controlled source I'd use a SMU. It's just that it is kind of embarrassing that the PSU performs worse (w.r.t CC mode startup) than 5 decades old design using two opamp control with OR-ing diodes.